CD4029BF3A中文资料德州仪器数据手册PDF规格书

Features:

® Medium-speed operation . . . 8 MHz (typ.)

@Cy_ = 50 pF and Vpp—Vgg = 10 V

# Multi-package parallel clocking for synchronous

high speed output response or ripple clocking

for slow clock input rise and fall times

= “Preset Enable” and individual “Jam” inputs provided

® Binary or decade up/down counting

= BCD outputs in decade mode

® 100% tested for quiescent current at 20 V

® 5.V, 10-V, and 15-V parametric ratings -

® Standardized, symmetrical output charac-

teristics

® Maximum input current of 1 uA at 18 V

over full package-temperature range;

100 nA at 18 V and 26°C

® Noise margin (over full package-tempera-

ture range)

1VatVpp= 6V

2VatVpp=10V

25VatVpp=15V

® Meets all requirements of JEDEC Tentative

Standard No. 138, “Standard Specifications

for Description of ‘B’ Series CMOS Devices