Dual J-K Master/Slave Flip-Flop with Set and Reset

General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edg

文件：68.79 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual J-K Master/Slave Flip-Flop with Set and Reset

ONSEMI

安森美半导体

Package：16-DIP（0.300"，7.62mm）；包装：管件 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16DIP

ONSEMI

安森美半导体

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

文件：64.709 Kbytes 页数：5 Pages

PHI

PHI

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • High reliability, achieved by the DHD structure • Allowing to insert to a 5 mm pitch hole • Finely divided zener-voltage rank • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 39 V

文件：76.65 Kbytes 页数：6 Pages

PANASONIC

松下

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • High reliability, achieved by the DHD structure • Allowing to insert to a 5 mm pitch hole • Finely divided zener-voltage rank • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 39 V

文件：76.65 Kbytes 页数：6 Pages

PANASONIC

松下