丝印：CM0107B；Package：SO；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

文件：1.1513 Mbytes 页数：21 Pages

TI

德州仪器

丝印：CM0107B；Package：TSSOP；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

文件：1.1513 Mbytes 页数：21 Pages

TI

德州仪器

丝印：CM0107B；Package：TSSOP；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

文件：1.1513 Mbytes 页数：21 Pages

TI

德州仪器

丝印：CM0107B；Package：TSSOP；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

文件：1.1513 Mbytes 页数：21 Pages

TI

德州仪器

CMOS 4 x 4 Multiport Register

Description The CD40108BMS is a 4 x 4 multiport register containing four 4-bit registers, write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high-imp

文件：157.37 Kbytes 页数：11 Pages

INTERSIL

CMOS 4 x 4 Multiport Register

Description The CD40108BMS is a 4 x 4 multiport register containing four 4-bit registers, write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high-imp

文件：157.37 Kbytes 页数：11 Pages

INTERSIL

CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

文件：885.65 Kbytes 页数：19 Pages

TI

德州仪器

丝印：CD40109BE；Package：PDIP；CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

文件：885.65 Kbytes 页数：19 Pages

TI

德州仪器

丝印：CD40109BE；Package：PDIP；CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

文件：885.65 Kbytes 页数：19 Pages

TI

德州仪器

丝印：CD40109BF；Package：CDIP；CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

文件：885.65 Kbytes 页数：19 Pages

TI

德州仪器