CMOS 18-Stage Static Register

Features • High-Voltage Type (20V Rating) • Fully Static Operation • Shifting Rates Up to 12MHz at 10V (typ) • Permanent Register Storage with Clock Line High or Low - No Information Recirculation Required • 100% Tested for Quiescent Current at 20V • Standardized, Symmetrical Output Cha

文件：101.57 Kbytes 页数：8 Pages

SYC

CMOS 18-Stage Static Shift Register

Features: = Fully st operation = Shifting rates up to 12 MHz @ 10 V (typ) Pormanont register storage with clock fine high or low — no information recirculation required = 100% tested for quiescent current at 20 V = Standardized, symmetrical output characteristics #5V, 10-V, and 16-V par

文件：464.18 Kbytes 页数：9 Pages

TI

德州仪器

丝印：CD4006BF3A；Package：CDIP；CMOS 18-Stage Static Shift Register

Features: = Fully st operation = Shifting rates up to 12 MHz @ 10 V (typ) Pormanont register storage with clock fine high or low — no information recirculation required = 100% tested for quiescent current at 20 V = Standardized, symmetrical output characteristics #5V, 10-V, and 16-V par

文件：464.18 Kbytes 页数：9 Pages

TI

德州仪器

丝印：CD4006BF3A；Package：CDIP；CMOS 18-Stage Static Shift Register

Features: = Fully st operation = Shifting rates up to 12 MHz @ 10 V (typ) Pormanont register storage with clock fine high or low — no information recirculation required = 100% tested for quiescent current at 20 V = Standardized, symmetrical output characteristics #5V, 10-V, and 16-V par

文件：464.18 Kbytes 页数：9 Pages

TI

德州仪器

CMOS 18-Stage Static Shift Register

Features: = Fully st operation = Shifting rates up to 12 MHz @ 10 V (typ) Pormanont register storage with clock fine high or low — no information recirculation required = 100% tested for quiescent current at 20 V = Standardized, symmetrical output characteristics #5V, 10-V, and 16-V par

文件：464.18 Kbytes 页数：9 Pages

TI

德州仪器

CMOS 18-Stage Static Register

Description CD4006BMS types are composed of 4 separate shift register sections: two sections of four stages and two sections of five stages with an output tap at the fourth stage. Each section has an independent single-rail data path. A common clock signal is used for all stages. Data are shifte

文件：77.56 Kbytes 页数：8 Pages

INTERSIL

CMOS Dual Complementary Pair Plus Inverter

Description CD4007BMS types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. Features • High-Voltage Type (20V Rating) • Standardized Symmetrical Output Characteristics • Medium Speed Operation - tPHL, tPLH = 30 ns (typ) at 10V • 100 Tes

文件：104.81 Kbytes 页数：9 Pages

INTERSIL

Dual Complementary Pair Plus Inverter

General Description The CD4007C consists of three complementary pairs of N and P-channel enhancement mode MOS transistors suitable for series/shunt applications. All inputs are protected from static discharge by diode clamps to VDDand VSS. For proper operation the voltages at all pins must b

文件：49.46 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Dual Complementary Pair Plus Inverter

General Description The CD4007C consists of three complementary pairs of N and P-channel enhancement mode MOS transistors suitable for series/shunt applications. All inputs are protected from static discharge by diode clamps to VDDand VSS. For proper operation the voltages at all pins must b

文件：49.46 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Dual Complementary Pair Plus Inverter

General Description The CD4007C consists of three complementary pairs of N and P-channel enhancement mode MOS transistors suitable for series/shunt applications. All inputs are protected from static discharge by diode clamps to VDDand VSS. For proper operation the voltages at all pins must b

文件：49.46 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体