CD4006BMS中文资料INTERSIL数据手册PDF规格书

描述 Description

CD4006BMS types are composed of 4 separate shift register sections: two sections of four stages and two sections of five stages with an output tap at the fourth stage. Each section has an independent single-rail data path.

A common clock signal is used for all stages. Data are shifted to the next stages on negative-going transitions of the clock. Through appropriate connections of inputs and outputs, multiple register sections of 4, 5, 8, and 9 stages or single register sections of 10, 12, 13, 14, 16, 17 and 18 stages can be implemented using one CD4006BMS package. Longer shift register sections can be assembled by using more than one CD4006BMS.

特性 Features

• High-Voltage Type (20V Rating)

• Fully Static Operation

• Shifting Rates Up to 12MHz at 10V (typ)

• Permanent Register Storage with Clock Line High or

   Low - No Information Recirculation Required

• 100 Tested for Quiescent Current at 20V

• Standardized, Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full

   Package-Temperature Range; 100nA at 18V and +25oC

• Noise Margin (Full Package-Temperature Range):

   - 1V at VDD = 5V

   - 2V at VDD = 10V

   - 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standards No. 13B,

   “Standard Specifications for Description of “B” Series CMOS Devices”

Applications

• Serial Shift Registers

• Frequency Division

• Time Delay Circuits