ECL/PECL 1:9 Differential Clock Driver with Enable

DESCRIPTION The AZ10/100LVE111E is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q¯ outputs HIGH

文件：103.79 Kbytes 页数：6 Pages

AZM

ECL/PECL 1:9 Differential Clock Driver with Enable

DESCRIPTION The AZ10/100LVE111E is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q¯ outputs HIGH

文件：103.79 Kbytes 页数：6 Pages

AZM

ECL/PECL 1:9 Differential Clock Driver

DESCRIPTION The AZ10/100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. FEATURES • Operating Range of 3.0V to 5.5V • Low Skew • Guaranteed Skew Spec • Differential Design • VBB Out

文件：84.71 Kbytes 页数：6 Pages

AZM

ECL/PECL 1:9 Differential Clock Driver

DESCRIPTION The AZ10/100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. FEATURES • Operating Range of 3.0V to 5.5V • Low Skew • Guaranteed Skew Spec • Differential Design • VBB Out

文件：84.71 Kbytes 页数：6 Pages

AZM

ECL/PECL 1:4, 1:5 Differential Clock Driver

DESCRIPTION The AZ100LVE210 is a low skew 1:4, 1:5 fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The AZ100LVE210 offers two selectable clock inputs allowing redundant or test clocks to be incorpo

文件：71.9 Kbytes 页数：5 Pages

AZM

ECL/PECL 1:4, 1:5 Differential Clock Driver

DESCRIPTION The AZ100LVE210 is a low skew 1:4, 1:5 fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The AZ100LVE210 offers two selectable clock inputs allowing redundant or test clocks to be incorpo

文件：71.9 Kbytes 页数：5 Pages

AZM

ECL/PECL 2:8 Differential Clock Driver

DESCRIPTION The AZ100LVE310 is a low skew 2:8 fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The AZ100LVE310 offers two selectable clock inputs allowing redundant or test clocks to be incorporated

文件：71.92 Kbytes 页数：5 Pages

AZM

ECL/PECL 2:8 Differential Clock Driver

[ARIZONA MICROTEK, INC.] DESCRIPTION The AZ100LVE310 is a low skew 2:8 fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The AZ100LVE310 offers two selectable clock inputs allowing redundant or test

文件：146.36 Kbytes 页数：5 Pages

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未分类制造商

ECL/PECL 2:8 Differential Clock Driver

[ARIZONA MICROTEK, INC.] DESCRIPTION The AZ100LVE310 is a low skew 2:8 fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The AZ100LVE310 offers two selectable clock inputs allowing redundant or test

文件：146.36 Kbytes 页数：5 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

ECL/PECL 2:8 Differential Clock Driver

DESCRIPTION The AZ100LVE310 is a low skew 2:8 fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The AZ100LVE310 offers two selectable clock inputs allowing redundant or test clocks to be incorporated

文件：71.92 Kbytes 页数：5 Pages

AZM