ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable

DESCRIPTION The AZ100LVEL16VT is a specialized oscillator gain stage with high gain output buffer including an enable. The QHG/Q¯ HG outputs have a voltage gain several times greater than the Q/Q¯ outputs. FEATURES • High Bandwidth for ≥1GHz • Similar Operation as AZ100LVEL16VR except in

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Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable

DESCRIPTION The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain output buffer including an enable. FEATURES • High Bandwidth for ≥1GHz • Similar Operation as AZ100EL16VR except with selectable data input pairs • Operating Range of 3.0V

文件：93.7 Kbytes 页数：9 Pages

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Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable

DESCRIPTION The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain output buffer including an enable. FEATURES • High Bandwidth for ≥1GHz • Similar Operation as AZ100EL16VR except with selectable data input pairs • Operating Range of 3.0V

文件：93.7 Kbytes 页数：9 Pages

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Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable

DESCRIPTION The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain output buffer including an enable. FEATURES • High Bandwidth for ≥1GHz • Similar Operation as AZ100EL16VR except with selectable data input pairs • Operating Range of 3.0V

文件：93.7 Kbytes 页数：9 Pages

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ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100LVEL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple LVEL32’s in a system. FEATURES • Operat

文件：178.01 Kbytes 页数：8 Pages

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ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100LVEL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple LVEL32’s in a system. FEATURES • Operat

文件：178.01 Kbytes 页数：8 Pages

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ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

文件：104.2 Kbytes 页数：6 Pages

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ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

文件：104.21 Kbytes 页数：6 Pages

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ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100LVEL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple LVEL32’s in a system. FEATURES • Operat

文件：178.01 Kbytes 页数：8 Pages

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ECL/PECL 첨4 Divider

DESCRIPTION The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple LVEL33’s in a system. FEATU

文件：127.85 Kbytes 页数：10 Pages

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