Axcelerator Family FPGAs

文件：13.34193 Mbytes 页数：262 Pages

Microsemi

美高森美

Axcelerator Family FPGAs

文件：13.34193 Mbytes 页数：262 Pages

Microsemi

美高森美

丝印：AX1250；2A Sink/Source Bus Termination Regulator

 GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：753.8 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

丝印：AX1255；2A Sink/Source Bus Termination Regulator

 GENERAL DE S CRIPTION The AX1255 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：738.14 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

2A Sink/Source Bus Termination Regulator

 GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：753.8 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

2A Sink/Source Bus Termination Regulator

 GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：753.8 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

2A Sink/Source Bus Termination Regulator

 GENERAL DE S CRIPTION The AX1255 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：738.14 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

2A Sink/Source Bus Termination Regulator

 GENERAL DE S CRIPTION The AX1255 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：738.14 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

Flexible expansion through MiniPCI

文件：200.38 Kbytes 页数：1 Pages

AXIOMTEK

艾讯科技

Axcelerator Family FPGAs

文件：2.34721 Mbytes 页数：226 Pages

Actel

Actel Corporation