2A Sink/Source Bus Termination Regulator

 GENERAL DE S CRIPTION The AX1255 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：738.14 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

2A Sink/Source Bus Termination Regulator

 GENERAL DE S CRIPTION The AX1255 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：738.14 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

DUAL-CORE 64-BIT MIPS PROCESSOR

文件：122.43 Kbytes 页数：2 Pages

BOARDCOM

博通

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BOARDCOM

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文件：616.47 Kbytes 页数：4 Pages

EATON

伊顿