丝印：AX1250；2A Sink/Source Bus Termination Regulator

 GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：753.8 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

丝印：AX1250；2A Sink/Source Bus Termination Regulator

 GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：753.8 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

2A Sink/Source Bus Termination Regulator

 GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：753.8 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

2A Sink/Source Bus Termination Regulator

 GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：753.8 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

Flexible expansion through MiniPCI

文件：200.38 Kbytes 页数：1 Pages

AXIOMTEK

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