1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 页数：60 Pages

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1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

文件：1.07463 Mbytes 页数：56 Pages

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1.2 GHz时钟分配IC，PLL内核，分频器，延迟调整，8路输出

AD9510提供多路输出时钟分配功能，并集成一个片内锁相环(PLL)内核。它具有低抖动和低相位噪声特性，能够极大地提升数据转换器的时钟性能。4路独立的LVPECL时钟输出和4路LVDS时钟输出工作频率分别为1.2 GHz和800 MHz。可选的CMOS时钟输出工作频率为250 MHz。\n\n PLL部分由可编程参考分频器(R)、低噪声鉴频鉴相器(PFD)、精密电荷泵(CP)和可编程反馈分频器(N)组成。将外部VCXO或VCO连接到CLK2和CLK2B引脚时，最高达1.6 GHz的PLL输出频率可以与输入参考REFIN同步。\n\n 时钟分配部分提供LVPECL输出和可编程 • 低相位噪声锁相环内核\n• 最高250 MHz的基准输入频率\n\n• 可编程双模预分频器\n\n• 可编程电荷泵(CP)电流\n\n• 独立的CP电源(VCPS)可扩展调整范围\n\n\n\n\n• 两路1.6 GHz差分时钟输入\n\n• 8个可编程分频器，1至32整数分频比\n\n• 用于输出到输出延迟粗调的相位选择\n\n• 4路独立的1.2 GHz LVPECL输出\n• 加性输出抖动：225 fs rms\n\n\n\n\n• 4路独立的800 MHz低压差模信号\n• (LVDS)或250 MHz互补金属氧化物半导体\n\n• (CMOS)时钟输出\n\n• 加性输出抖动：2;

ADI

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1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 页数：60 Pages

AD

亚德诺

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 页数：60 Pages

AD

亚德诺

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 页数：60 Pages

AD

亚德诺

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 页数：60 Pages

AD

亚德诺

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 页数：60 Pages

AD

亚德诺

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：597.01 Kbytes 页数：60 Pages

AD

亚德诺

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

文件：886.11 Kbytes 页数：56 Pages

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