丝印：AC11032；Package：SOIC；QUADRUPLE 2-INPUT POSITIVE-OR GATE

Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-m

文件：1.23403 Mbytes 页数：28 Pages

TI

德州仪器

丝印：AC11032；Package：SOP；QUADRUPLE 2-INPUT POSITIVE-OR GATE

Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-m

文件：1.23403 Mbytes 页数：28 Pages

TI

德州仪器

丝印：AC11032；Package：SOP；QUADRUPLE 2-INPUT POSITIVE-OR GATE

Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-m

文件：1.23403 Mbytes 页数：28 Pages

TI

德州仪器

丝印：AC11074；Package：SOIC；DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-μm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 3

文件：612.2 Kbytes 页数：18 Pages

TI

德州仪器

丝印：AC11074；Package：SOIC；DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-μm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 3

文件：612.2 Kbytes 页数：18 Pages

TI

德州仪器

丝印：AC11074；Package：SOIC；DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-μm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 3

文件：612.2 Kbytes 页数：18 Pages

TI

德州仪器

丝印：AC11086；Package：SOIC；QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N) description

文件：290.07 Kbytes 页数：9 Pages

TI

德州仪器

丝印：AC11086；Package：SOIC；QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N) description

文件：290.07 Kbytes 页数：9 Pages

TI

德州仪器

丝印：AC11240；Package：SOIC；OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-
m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (DW) and Shrink Small-

文件：420.85 Kbytes 页数：16 Pages

TI

德州仪器

丝印：AC11240；Package：SOIC；OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-
m Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (DW) and Shrink Small-

文件：420.85 Kbytes 页数：16 Pages

TI

德州仪器