15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

Features/Benefits • Fixed feedback path; 0ps input-to-output delay • 9 Selectable SMBus addresses; Multiple devices can share same SMBus segment • Separate VDDIO for outputs; allows maximum power savings • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL BW; minimizes ji

文件：439.18 Kbytes 页数：20 Pages

RENESAS

瑞萨

Fixed feedback path

文件：220.07 Kbytes 页数：19 Pages

IDT

15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

文件：227.73 Kbytes 页数：19 Pages

IDT

15-output DB1900Z Derivative

The 9ZXL1530 is a low-power version of the 9ZX21501. It has 15 low-power HCSL-compatible outputs and meets all the performance requirements of the Intel DB1900Z specification, while reducing power consumption more than 50% from the original IDT9ZX21501. It is suitable for PCI-Express Gen1/2/3 or 15 - 0.7V low-power HCSL output pairs\nSave power and board space - no Rp\nSpace-saving 64-pin QFN package\nFixed feedback path for 0ps input-to-output delay\n9 Selectable SMBus Addresses\nPLL or bypass mode\nPLL can dejitter incoming clock\n100MHz or 133MHz PLL mode operation for PCIe and QPI/UPI a;

Renesas

瑞萨

丝印：ICS9ZXL1530BKL；Package：MLF；15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

Features/Benefits • Fixed feedback path; 0ps input-to-output delay • 9 Selectable SMBus addresses; Multiple devices can share same SMBus segment • Separate VDDIO for outputs; allows maximum power savings • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL BW; minimizes ji

文件：439.18 Kbytes 页数：20 Pages

RENESAS

瑞萨

丝印：ICS9ZXL1530BKL；Package：MLF；15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

Features/Benefits • Fixed feedback path; 0ps input-to-output delay • 9 Selectable SMBus addresses; Multiple devices can share same SMBus segment • Separate VDDIO for outputs; allows maximum power savings • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL BW; minimizes ji

文件：439.18 Kbytes 页数：20 Pages

RENESAS

瑞萨

15 to 19-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ LP-HCSL outputs eliminate up to 4 resistors per output pair ▪ 9 selectable SMBus addresses ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies ▪ Hardware/SMBus control of ZDB and FOB modes allow change without power cycle ▪ 8 OE# pins support PCIe CLKR

文件：1.05564 Mbytes 页数：35 Pages

RENESAS

瑞萨

15 to 19-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ LP-HCSL outputs eliminate up to 4 resistors per output pair ▪ 9 selectable SMBus addresses ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies ▪ Hardware/SMBus control of ZDB and FOB modes allow change without power cycle ▪ 8 OE# pins support PCIe CLKR

文件：1.05564 Mbytes 页数：35 Pages

RENESAS

瑞萨

15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

文件：227.73 Kbytes 页数：19 Pages

IDT

15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

文件：227.73 Kbytes 页数：19 Pages

IDT