9ZXL1231E中文资料12-Output DB1200ZL PCIe Zero-Delay/Fanout Clock Buffer数据手册Renesas规格书

描述 Description

The 9ZXL1231E is a second-generation, enhanced performance DB1200ZL differential buffer. The part is a pin-compatible upgrade to the 9ZXL1231A, while offering much improved phase jitter performance and increased system security features. A fixed external feedback maintains low drift for critical QPI/UPI applications.

特性 Features

LP-HCSL outputs; eliminate 24 resistors, save 41mm² of area
PCIe Gen 1–5 compliance
12 OE# pins; hardware control of each output
9 selectable SMBus addresses; multiple devices can share the same SMBus segment
Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
Spread spectrum compatible; tracks spreading input clock for EMI reduction
100MHz and 133.33MHz PLL Mode; UPI and legacy QPI support
9 x 9 mm 64-VFQFPN package; small board footprint

应用 Application

• 企业服务器