9ZXL0851E中文资料8-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer数据手册Renesas规格书

描述 Description

The 9ZXL0851E is a second-generation enhanced performance DB800ZL differential buffer. The part is a pin-compatible upgrade to the 9ZXL0851A, while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications.

特性 Features

• LP-HCSL outputs with 85Ω Zout; eliminate 32 resistors, save 64mm² of area
• PCIe Gen 1–5 compliance
• 8 OE# pins; hardware control of each output
• Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
• Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
• Spread spectrum compatible; tracks spreading input clock for EMI reduction
• 100MHz and 133.33MHz PLL mode; UPI and legacy QPI support
• 6 × 6 mm 48-VFQFPN package; small board footprint