9ZML1252E数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The 9ZML1252E is a second generation 2-input/12-output differential mux for Intel Purley and newer platforms. It exceeds the demanding DB1200ZL performance specifications and is backwards compatible to the 9ZML1232B. It utilizes Low Power HCSL-compatible outputs to reduce power consumption and termination resistors. It is suitable for PCI-Express Gen1-4 or QPI/UPI applications, and provides 2 configurable low-drift I2O settings, one for each input channel, to allow I2O tuning for various topologies.

特性 Features

2 configurable low-drift I2O delays up to 2.9ns; maintain transport delay for various topologies
LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors
9 selectable SMBus addresses; multiple devices can share same SMBus segment
Separate VDDIO for outputs; allows maximum power savings
PLL or Bypass Mode; PLL can dejitter incoming clock
Hardware or software-selectable PLL BW; minimizes jitter peaking in downstream PLLs
Spread spectrum compatible; tracks spreading input clock for EMI reduction
SMBus interface; software can modify device settings without hardware changes
10 x 10 mm 72-QFN package; small board footprint

应用 Application

• Xilinx Kintex-7 电源和时序
• Xilinx UltraScale+ RFSoC Gen 1/2 ZU2x/3x 电源和时序
• Xilinx Versal ACAP 电源和时序