| 型号 | 下载 订购 | 功能描述 | 制造商 上传企业 | LOGO |
|---|---|---|---|---|
9ZXL1231E | 12-Output DB1200ZL for PCIe Gen1?? and UPI 文件:267.38 Kbytes 页数:21 Pages | IDT | IDT | |
4 to 12-Output Buffers for PCIe Gen1–5 and UPI Features ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topolo 文件:1.35602 Mbytes 页数:34 Pages | RENESAS 瑞萨 | RENESAS | ||
4 to 12-Output Buffers for PCIe Gen1–5 and UPI Features ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topolo 文件:1.35602 Mbytes 页数:34 Pages | RENESAS 瑞萨 | RENESAS | ||
4 to 12-Output Buffers for PCIe Gen1–5 and UPI Features ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topolo 文件:1.35602 Mbytes 页数:34 Pages | RENESAS 瑞萨 | RENESAS | ||
4 to 12-Output Buffers for PCIe Gen1–5 and UPI Features ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topolo 文件:1.35602 Mbytes 页数:34 Pages | RENESAS 瑞萨 | RENESAS | ||
4 to 12-Output Buffers for PCIe Gen1–5 and UPI Features ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topolo 文件:1.35602 Mbytes 页数:34 Pages | RENESAS 瑞萨 | RENESAS | ||
4 to 12-Output Buffers for PCIe Gen1–5 and UPI Features ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topolo 文件:1.35602 Mbytes 页数:34 Pages | RENESAS 瑞萨 | RENESAS | ||
12-Output DB1200ZL for PCIe Gen1?? and UPI 文件:267.38 Kbytes 页数:21 Pages | IDT | IDT | ||
12-Output DB1200ZL for PCIe Gen1?? and UPI 文件:267.38 Kbytes 页数:21 Pages | IDT | IDT | ||
12-Output DB1200ZL for PCIe Gen1?? and UPI 文件:267.38 Kbytes 页数:21 Pages | IDT | IDT |
技术参数
- Clock Spec.:
DB1200ZL v0.8
- Diff. Outputs:
12
- Diff. Output Signaling:
LP-HCSL
- Output Enable (OE) Pins:
12
- Output Freq Range (MHz):
1 - 400
- Diff. Inputs:
1
- Diff. Input Signaling:
HCSL
- Accepts Spread Spec Input:
Yes
- Power Consumption Typ (mW):
481
- Advanced Features:
SW PLL mode control
- App Jitter Compliance:
25G EDR
- Lead Count (#):
64
- Package Area (mm²):
81
- Chipset Name:
C600
- Pkg. Type:
VFQFPN
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
RENESAS(瑞萨)/IDT |
2447 |
VFQFPN-64(9x9) |
315000 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
询价 | ||
RENESAS(瑞萨)/IDT |
2021+ |
VFQFPN-64(9x9) |
499 |
询价 | |||
Renesas |
23+ |
S/N |
20000 |
公司主营品牌长期供应原装现货可含税提供技术 |
询价 | ||
RENESAS |
2034+ |
NA |
2391 |
原装正品 价格极优 |
询价 | ||
RENESAS |
新年份 |
NA |
12000 |
原装正品现货,可出样品可开税票 |
询价 | ||
Renesas Electronics America In |
25+ |
- |
9350 |
独立分销商 公司只做原装 诚心经营 免费试样正品保证 |
询价 | ||
RENESAS |
24+ |
con |
35960 |
查现货到京北通宇商城 |
询价 | ||
Renesas |
25+ |
电联咨询 |
7800 |
公司现货,提供拆样技术支持 |
询价 | ||
Renesas(瑞萨) |
25+ |
- |
500000 |
源自原厂成本,高价回收工厂呆滞 |
询价 | ||
Renesas Electronics America In |
24+ |
/ |
3000 |
全新、原装 |
询价 |
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