Programmable Slew rate for each output

Description The 9FGV0241 is a 2-output very low power frequency generator for PCIe Gen 1, 2, 3 and 4 applications with integrated output terminations providing Zo=100. The device has 2 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

文件：230.11 Kbytes 页数：15 Pages

IDT

2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

文件：616.42 Kbytes 页数：15 Pages

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2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR

文件：230.26 Kbytes 页数：15 Pages

IDT

2-output 1.8 V PCIe Gen1-4 Clock Generator with Zo=100 ohms

The 9FGV0241 is a 2-output very low power frequency generator for PCIe Gen1–4 applications with integrated output terminations providing Zo=100 Ω. The device has 2 output enables for clock management and supports 2 different spread spectrum levels in addtion to spread off. PCIe Gen1–4 compliant\nIntegrated terminations provide 100 Ω differential Zo: reduced component count and board space\n1.8 V operation: reduced power consumption\nOE# pins: support DIF power management\nLP-HCSL differential clock outputs: reduced power and board space\nProgrammable slew rate for eac;

Renesas

瑞萨

丝印：LOT241AL；Package：24-VFQFPN；2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

文件：616.42 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：LOT241AL；Package：24-VFQFPN；2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

文件：616.42 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：LOT241AL；Package：24-VFQFPN；2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

文件：616.42 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：LOT241AL；Package：24-VFQFPN；2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

文件：616.42 Kbytes 页数：15 Pages

RENESAS

瑞萨

2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR

文件：230.26 Kbytes 页数：15 Pages

IDT

2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

文件：290.13 Kbytes 页数：16 Pages

IDT