型号：9FGV0241AKILF；Package：24-VFQFPN；2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

文件：616.42 Kbytes 页数：15 Pages

瑞萨

型号：9FGV0241AKILFT；Package：24-VFQFPN；2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

文件：616.42 Kbytes 页数：15 Pages

瑞萨

型号：9FGV0241AKLF；Package：24-VFQFPN；2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

文件：616.42 Kbytes 页数：15 Pages

瑞萨

型号：9FGV0241AKLFT；Package：24-VFQFPN；2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

文件：616.42 Kbytes 页数：15 Pages

瑞萨