6-output 3.3V PCIe Clock Generator

文件：326.25 Kbytes 页数：19 Pages

IDT

control input polarity

文件：325.98 Kbytes 页数：19 Pages

IDT

6-Output 3.3V PCIe Gen1–5 Clock Generator

The 9FGL0641/51 devices are 6-output 3.3V PCIe Gen1–5 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0641/51 supports PCIe Gen1–5 Common Clocked architectures (CC), P • PCIe Gen1–5 CC-compliant\n• Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output\n• SMBus-selectable CC/SRIS -0.25% spread\n• Easy AC-coupling to other logic families, see application note AN-891.\n• Space saving 5 × 5 mm 40-VFQFPN;

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瑞萨

3.3V PCIe Gen1–5 Clock Generator Family

Features ▪ Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output ▪ 112–206 mW typical power consumption (at 3.3V) ▪ VDDIO rail allows 35 power savings at optional 1.05V (9FGL06 and 9FGL08 only) ▪ Devices contain default configuration; SMBus not required ▪ SMBus-select

文件：1.35998 Mbytes 页数：37 Pages

RENESAS

瑞萨

3.3V PCIe Gen1–5 Clock Generator Family

Features ▪ Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output ▪ 112–206 mW typical power consumption (at 3.3V) ▪ VDDIO rail allows 35 power savings at optional 1.05V (9FGL06 and 9FGL08 only) ▪ Devices contain default configuration; SMBus not required ▪ SMBus-select

文件：1.35998 Mbytes 页数：37 Pages

RENESAS

瑞萨

3.3V PCIe Gen1–5 Clock Generator Family

Features ▪ Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output ▪ 112–206 mW typical power consumption (at 3.3V) ▪ VDDIO rail allows 35 power savings at optional 1.05V (9FGL06 and 9FGL08 only) ▪ Devices contain default configuration; SMBus not required ▪ SMBus-select

文件：1.35998 Mbytes 页数：37 Pages

RENESAS

瑞萨

3.3V PCIe Gen1–5 Clock Generator Family

Features ▪ Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output ▪ 112–206 mW typical power consumption (at 3.3V) ▪ VDDIO rail allows 35 power savings at optional 1.05V (9FGL06 and 9FGL08 only) ▪ Devices contain default configuration; SMBus not required ▪ SMBus-select

文件：1.35998 Mbytes 页数：37 Pages

RENESAS

瑞萨

3.3V PCIe Gen1–5 Clock Generator Family

Features ▪ Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output ▪ 112–206 mW typical power consumption (at 3.3V) ▪ VDDIO rail allows 35 power savings at optional 1.05V (9FGL06 and 9FGL08 only) ▪ Devices contain default configuration; SMBus not required ▪ SMBus-select

文件：1.35998 Mbytes 页数：37 Pages

RENESAS

瑞萨

6-output 3.3V PCIe Clock Generator

文件：326.25 Kbytes 页数：19 Pages

IDT

6-output 3.3V PCIe Clock Generator

文件：326.25 Kbytes 页数：19 Pages

IDT