9FGL0641CKILF集成电路（IC）的应用特定时钟/定时规格书PDF中文资料

特性 Features

▪ Integrated terminations for 100Ω and 85Ω systems save 4

resistors per output

▪ 112–206 mW typical power consumption (at 3.3V)

▪ VDDIO rail allows 35 power savings at optional 1.05V

(9FGL06 and 9FGL08 only)

▪ Devices contain default configuration; SMBus not required

▪ SMBus-selectable features allows optimization to customer

requirements:

• Input polarity and pull-up/pull-downs

• Output slew rate and amplitude

• Output impedance (33Ω, 85Ω or 100Ω) for each output

▪ Contact factory for customized default configurations

▪ 25MHz input frequency

▪ OE# pins support PCIe CLKREQ# function

▪ Pin-selectable SRnS 0, CC 0 and CC/SRIS -0.5 spread

▪ SMBus-selectable CC/SRIS -0.25 spread

▪ Clean switching between the CC/SRIS spread settings

▪ DIF outputs blocked until PLL is locked; clean system start-up

▪ Two selectable SMBus addresses

▪ Space saving packages:

• 4 × 4 mm 24-VFQFPN (9FGL02x1)

• 5 × 5 mm 32-VFQFPN (9FGL04x1)

• 5 × 5 mm 40-VFQFPN (9FGL06x1)

• 6 × 6 mm 48-VFQFPN (9FGL08x1)