Six Output Differential Buffer for PCIe Gen 2

Description The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize per

文件：337.06 Kbytes 页数：15 Pages

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Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes 页数：14 Pages

IDT

6-output Differential Buffer For PCIe Gen2

The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems 6 - 0.7 V current mode differential output pairs (HCSL)\nCLKREQ# pin for outputs 1 and 4/ supports Express Card applications\nPLL or bypass mode/PLL can dejitter incoming clock\nSelectable PLL bandwidth/minimizes jitter peaking in downstream PLL's\nSpread Spectrum Compatible/tracks spreading input c;

Renesas

瑞萨

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes 页数：14 Pages

IDT

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes 页数：14 Pages

IDT

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes 页数：14 Pages

IDT

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes 页数：14 Pages

IDT

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes 页数：14 Pages

IDT

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes 页数：14 Pages

IDT

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes 页数：14 Pages

IDT