JESD204B/C Compliant Fanout Buffer and Divider

Description The 8V79S683 is a fully integrated, clock and SYSREF signal fanout buffer for JESD204B/C applications. It is designed as a high-performance clock and converter synchronization solution for wireless base station radio equipment boards with JESD204B/C subclass 0, 1, and 2 compliance

文件：1.97108 Mbytes 页数：53 Pages

RENESAS

瑞萨

JESD204B/C Compliant Fanout Buffer and Divider

The 8V79S683 is a fully integrated, clock and SYSREF signal fanout buffer for JESD204B/C applications. It is designed as a high-performance clock and converter synchronization solution for wireless base station radio equipment boards with JESD204B/C subclass 0, 1, and 2 compliance. The main function • Distribution, fanout, phase-delay of clock and SYSREF signals\n• Very low output noise floor: -158.8dBc/Hz noise floor (245.76MHz)\n• Supports clock frequencies up to 3GHz, including clock output frequencies of 983.04MHz, 491.52MHz, 245.76MHz, and 122.88MHz\n• Four output channels with a total of ;

Renesas

瑞萨

Package：64-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：VFQFPN 9.00X9.00X0.90 MM, 0.50MM

Renesas Electronics America Inc