8V79S683中文资料JESD204B/C Compliant Fanout Buffer and Divider数据手册Renesas规格书

描述 Description

The 8V79S683 is a fully integrated, clock and SYSREF signal fanout buffer for JESD204B/C applications. It is designed as a high-performance clock and converter synchronization solution for wireless base station radio equipment boards with JESD204B/C subclass 0, 1, and 2 compliance. The main function of the device is the distribution and fanout of high-frequency clocks and low-frequency system reference signals generated by a JESB204B clock generator such as the IDT 8V19N490, extending its fanout capabilities and providing additional phase-delay. The 8V79S683 is optimized to deliver very low phase noise clocks and precise, phase-adjustable SYSREF synchronization signals. Low-skew outputs, low device-to-device skew characteristics and fast output rise/fall times help the system design to achieve deterministic clock and SYSREF phase relationship across devices.

The device distributes the input clock (CLK) and JESD204B SYSREF signals (REF) to four fanout channels. Input clock signals can be frequency divided and are fanned-out to multiple clock (QCLK_y) and SYSREF (QREF_r) outputs. Configurable phase-delay circuits are available for both clock and SYSREF signals. The propagation delays in all signal paths are fully deterministic to support fixed phase relationships between clock and SYSREF signals within one device. The device facilitates synchronization between frequency dividers within the device and across multiple devices, removing phase ambiguity introduced in dividers between power and configuration cycles.

特性 Features

• Distribution, fanout, phase-delay of clock and SYSREF signals
• Very low output noise floor: -158.8dBc/Hz noise floor (245.76MHz)
• Supports clock frequencies up to 3GHz, including clock output frequencies of 983.04MHz, 491.52MHz, 245.76MHz, and 122.88MHz
• Four output channels with a total of 16 differential outputs
• Each channel contains frequency dividers and clock phase delay circuits
• Phase alignment mode across multiple buffers with any frequency divider setting
• Flexible differential outputs (LVDS/LVPECL/amplitude configurable)
• Configuration through 3-wire SPI interface
• Supply voltage:
• 3.3V core and signal I/O
• 1.8V Digital control SPI I/O (3.3V-tolerant inputs)

应用 Application

• 5G MIMO无线传送: RF + 定时
• 手持式超声扫描仪