1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 3.3V Fanout Buffer

Features • Ten single-ended LVCMOS outputs, 7 typical output impedance • Selectable CLK0 and CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum input/output frequency: 150MHz • Output skew: 350ps (maximum) • 3.3V input, 3.3V outputs

文件：334.11 Kbytes 页数：12 Pages

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1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

Features • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance • LVPECL clock input pair • PCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL • Maximum input frequency: 250MHz • Output skew: 120ps (maximum) • Part-to-part skew: 700ps (maximum) • Multiple freq

文件：438.79 Kbytes 页数：16 Pages

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1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

Features • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance • Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum input frequency: 250MHz • Bank skew: 30ps (maximum) • Output skew: 175ps (maximum)

文件：411.15 Kbytes 页数：15 Pages

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1-to-10 Low Skew, LVCMOS/LVTTL Fanout Buffer

文件：211.23 Kbytes 页数：14 Pages

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1-to-10 Low Skew, ÷1,÷2 LVCMOS/LVTTL 3.3V Fanout Buffer

The 87946I is a low skew, ÷1, ÷2 LVCMOS Fanout Buffer. The 87946I has two selectable single ended clock inputs. The 87946I has two selectable single ended clock inputs. The single ended clock inputs accept LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50Ω serie Ten single-ended LVCMOS outputs, 7Ω typical output impedance\nSelectable CLK0 and CLK1 LVCMOS clock inputs\nCLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL\nMaximum input/output frequency: 150MHz\nOutput skew: 350ps (maximum)\n3.3V input, 3.3V outputs\n-40°C to 85°C ambient ope;

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1-to-10 Low Skew, ÷1,÷2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

The 87946I-01 is a low skew, ÷1, ÷2 Fanout Buffer. The 87946I-01 has one LVPECL clock input pair. The PCLK/nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout Ten single ended LVCMOS/LVTTL outputs, 7Ω typical output impedance\nLVPECL clock input pair\nPCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL\nMaximum input frequency: 250MHz\nOutput skew: 120ps (maximum)\nPart-to-part skew: 700ps (maximum)\nMultiple frequency skew: 320ps (maximum)\;

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1-to-10 Low Skew,÷1,÷2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

The 87946I-147 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Fanout Buffer. The 87946I-147 has two selectable single-ended clock inputs. The single-ended clock inputs accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission • Ten single-ended LVCMOS/LVTTL outputs, 7Ω typical output impedance\n• Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs\n• CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL\n• Maximum input frequency: 250MHz\n• Bank skew: 30ps (maximum)\n• Output skew: 175ps (maximum)\n• Part-to-par;

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