87946I-01中文资料1-to-10 Low Skew, ÷1,÷2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer数据手册Renesas规格书

描述 Description

The 87946I-01 is a low skew, ÷1, ÷2 Fanout Buffer. The 87946I-01 has one LVPECL clock input pair. The PCLK/nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines. The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The 87946I-01 is characterized at 3.3V core/3.3V output and 3.3V core/2.5V output. Guaranteed bank, output and part-to-part skew characteristics make the 87946I-01 ideal for those clock distribution applications demanding well defined performance and repeatability.

特性 Features

Ten single ended LVCMOS/LVTTL outputs, 7Ω typical output impedance
LVPECL clock input pair
PCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL
Maximum input frequency: 250MHz
Output skew: 120ps (maximum)
Part-to-part skew: 700ps (maximum)
Multiple frequency skew: 320ps (maximum)
Additive phase jitter, RMS: 0.19ps (typical)
3.3V core, 3.3V or 2.5V output supply modes-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6) packages