1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

Features • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance • LVPECL clock input pair • PCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL • Maximum input frequency: 250MHz • Output skew: 120ps (maximum) • Part-to-part skew: 700ps (maximum) • Multiple freq

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1-to-10 Low Skew, ÷1,÷2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

The 87946I-01 is a low skew, ÷1, ÷2 Fanout Buffer. The 87946I-01 has one LVPECL clock input pair. The PCLK/nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout Ten single ended LVCMOS/LVTTL outputs, 7Ω typical output impedance\nLVPECL clock input pair\nPCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL\nMaximum input frequency: 250MHz\nOutput skew: 120ps (maximum)\nPart-to-part skew: 700ps (maximum)\nMultiple frequency skew: 320ps (maximum)\;

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瑞萨

DIP-28

TOSHIBA

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