Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer

Features • Fully integrated PLL • Fourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync • Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accep

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Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer

文件：467.82 Kbytes 页数：20 Pages

IDT

Fully integrated PLL

文件：400.81 Kbytes 页数：19 Pages

IDT

Low Skew, 1-to-12 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer

The 87973I-147 is a LVCMOS/LVTTL clock generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The 87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. The 87973I-147 is a highly flexible device. The three selectable inputs (1 different Fully integrated PLL\nFourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync\nSelectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs\nCLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL\nCLK, nCLK pair can accept the following different;

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瑞萨

Low Skew, 1-to-12 LVCMOS/ LVTTL Clock Multiplier/ Zero Delay Buffer

文件：467.82 Kbytes 页数：20 Pages

IDT