87946I-147数据手册Renesas中文资料规格书

描述 Description

The 87946I-147 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Fanout Buffer. The 87946I-147 has two selectable single-ended clock inputs. The single-ended clock inputs accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines.

The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.

The 87946I-147 is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply mode. Guaranteed bank, output and part-to-part skew characteristics make the 87946I-147 ideal for those clock distribution applications demanding well defined performance and repeatability.

特性 Features

• Ten single-ended LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs
• CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL
• Maximum input frequency: 250MHz
• Bank skew: 30ps (maximum)
• Output skew: 175ps (maximum)
• Part-to-part skew: 850ps (maximum)
• Multiple frequency skew: 200ps (maximum)
• 3.3V core, 3.3V or 2.5V output supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package