1:1 Differential-to-LVDS Zero Delay Clock Generator

Features • One differential LVDS output pair and one differential feedback output pair • One differential clock input pair • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL • Input frequency range: 62.5MHz to 1GHz • Output frequency range: 62.5MHz to

文件：533.36 Kbytes 页数：16 Pages

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瑞萨

1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：401.42 Kbytes 页数：17 Pages

IDT

Differential-to-LVDS Zero Delay Clock Generator

The 874S02I is a highly versatile 1:1 Differentialto- LVDS Clock Generator and a member of the family of High Performance Clock Solutions from IDT. The 874S02I has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider, and has an output frequency range of 62.5MHz • One differential LVDS output pair and one differential feedback output pair\n• One differential clock input pair\n• CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL\n• Input frequency range: 62.5MHz to 1GHz\n• Output frequency range: 62.5MHz to 1GHz\n• VCO ra;

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One differential clock input pair

文件：4.08865 Mbytes 页数：16 Pages

IDT