One differential clock input pair

文件：4.08865 Mbytes 页数：16 Pages

IDT

1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：401.42 Kbytes 页数：17 Pages

IDT

1:1 Differential-to-LVDS Zero Delay Clock Generator

Features • One differential LVDS output pair and one differential feedback output pair • One differential clock input pair • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL • Input frequency range: 62.5MHz to 1GHz • Output frequency range: 62.5MHz to

文件：533.36 Kbytes 页数：16 Pages

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1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：401.42 Kbytes 页数：17 Pages

IDT