MALE/FEMALE THREADED STANDOFFS

文件：310.8 Kbytes 页数：1 Pages

KEYSTONE

Keystone Electronics Corp.

MSD 2-Step Launch Control for GM LS Series Engines

文件：107.02 Kbytes 页数：2 Pages

MALLORY

包装：散装 类别：五金件，紧固件，配件 板垫片，支座 描述：HEX STANDOFF #8-32 ALUMINUM 1/4\

Keystone Electronics

丝印：332AI01L；Package：SOIC；÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator

FEATURES • One ÷2 differential 2.5V/3.3V LVPECL / ECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 500MHz • Maximum input frequency: 1GHz • Translates any single ended inpu

文件：531.21 Kbytes 页数：15 Pages

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瑞萨

丝印：332AI01L；Package：SOIC；÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator

FEATURES • One ÷2 differential 2.5V/3.3V LVPECL / ECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 500MHz • Maximum input frequency: 1GHz • Translates any single ended inpu

文件：531.21 Kbytes 页数：15 Pages

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瑞萨

÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator

FEATURES • One ÷2 differential 2.5V/3.3V LVPECL / ECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 500MHz • Maximum input frequency: 1GHz • Translates any single ended inpu

文件：531.21 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：ICS7339AI11L；Package：TSSOP；Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator

FEATURES • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Tra

文件：386.47 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS7339AI11L；Package：TSSOP；Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator

FEATURES • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Tra

文件：386.47 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS7339AI11L；Package：SOIC；Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator

FEATURES • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Tra

文件：386.47 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS7339AI11L；Package：SOIC；Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator

FEATURES • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Tra

文件：386.47 Kbytes 页数：16 Pages

RENESAS

瑞萨