87339AMI-11LF集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

FEATURES

• Dual ÷2, ÷4 differential 3.3V LVPECL outputs;

Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs

• One differential CLK, nCLK input pair

• CLK, nCLK pair can accept the following differential

input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• Maximum clock input frequency: 1GHz

• Translates any single ended input signal (LVCMOS, LVTTL,

GTL) to LVPECL levels with resistor bias on nCLK input

• Output skew: 35ps (maximum)

• Part-to-part skew: 385ps (maximum)

• Bank skew: Bank A - 20ps (maximum)

Bank B - 20ps (maximum)

• Propagation delay: 2.1ns (maximum)

• LVPECL mode operating voltage supply range:

VCC = 3V to 3.6V, VEE = 0V

• Available in lead-free (RoHS 6) package