丝印：86004BIL；Package：TSSOP；15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer

FEATURES • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 15.625MHz to 62.5MHz • Input frequency range: 15.625MHz to 62.5MHz • VCO range: 250MHz to 500MHz • External

文件：475.78 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：86004BIL；Package：TSSOP；15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer

FEATURES • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 15.625MHz to 62.5MHz • Input frequency range: 15.625MHz to 62.5MHz • VCO range: 250MHz to 500MHz • External

文件：475.78 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：86004BGL；Package：TSSOP；15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer

FEATURES • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 15.625MHz to 62.5MHz • Input frequency range: 15.625MHz to 62.5MHz • VCO range: 250MHz to 500MHz • External

文件：419.15 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：86004BGL；Package：TSSOP；15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer

FEATURES • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 15.625MHz to 62.5MHz • Input frequency range: 15.625MHz to 62.5MHz • VCO range: 250MHz to 500MHz • External

文件：419.15 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：8601101EA；Package：CDIP；DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS

2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

文件：275.83 Kbytes 页数：12 Pages

TI

德州仪器

丝印：8607701CA；Package：CDIP；High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker

Features • Typical Propagation Delay = 17ns at VCC = 5V, CL = 15pF, TA = 25oC • Replaces LS180 Types • Easily Cascadable • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Op

文件：596.95 Kbytes 页数：17 Pages

TI

德州仪器

耳机插孔和插头

BRIM

包装：散装 类别：连接器，互连器件 电源连接器 描述：CONN POWER PLUG SOLDER EYELET

Switchcraft Inc.

包装：散装 类别：胶带，粘合剂，材料 胶带 描述：BLK 19 MM X 55 M BULK

3M

包装：散装 类别：五金件，紧固件，配件 其它 描述：CCTV TRI-FOOT BASE - BLACK

PanaVise