丝印：860；Package：SMC；Ultrafast power diode

文件：396.4 Kbytes 页数：10 Pages

WEEN

瑞能半导体

丝印：860；Package：10-pinTD；3-Channel Clock Distribution Buffer

文件：269.03 Kbytes 页数：12 Pages

SILABS

Silicon Laboratories

丝印：860；Package：10-pinTD；3-Channel Clock Distribution Buffer

文件：269.03 Kbytes 页数：12 Pages

SILABS

Silicon Laboratories

丝印：86004BIL；Package：TSSOP；15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer

FEATURES • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 15.625MHz to 62.5MHz • Input frequency range: 15.625MHz to 62.5MHz • VCO range: 250MHz to 500MHz • External

文件：475.78 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：86004BIL；Package：TSSOP；15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer

FEATURES • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 15.625MHz to 62.5MHz • Input frequency range: 15.625MHz to 62.5MHz • VCO range: 250MHz to 500MHz • External

文件：475.78 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：86004BGL；Package：TSSOP；15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer

FEATURES • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 15.625MHz to 62.5MHz • Input frequency range: 15.625MHz to 62.5MHz • VCO range: 250MHz to 500MHz • External

文件：419.15 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：86004BGL；Package：TSSOP；15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer

FEATURES • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 15.625MHz to 62.5MHz • Input frequency range: 15.625MHz to 62.5MHz • VCO range: 250MHz to 500MHz • External

文件：419.15 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：8601101EA；Package：CDIP；DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS

2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

文件：275.83 Kbytes 页数：12 Pages

TI

德州仪器

丝印：8607701CA；Package：CDIP；High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker

Features • Typical Propagation Delay = 17ns at VCC = 5V, CL = 15pF, TA = 25oC • Replaces LS180 Types • Easily Cascadable • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Op

文件：596.95 Kbytes 页数：17 Pages

TI

德州仪器

丝印：8607601EA；Package：CDIP；High-Speed CMOS Logic Presettable Counters

Features • ’HC161, ’HCT161 4-Bit Binary Counter, Asynchronous Reset • ’HC163, ’HCT163 4-Bit Binary Counter, Synchronous Reset • Synchronous Counting and Loading • Two Count Enable Inputs for n-Bit Cascading • Look-Ahead Carry for High-Speed Counting • Fanout (Over Temperature Range) - Sta

文件：383.44 Kbytes 页数：20 Pages

TI

德州仪器