丝印：8601101EA；Package：CDIP；DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS

2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

文件：275.83 Kbytes 页数：12 Pages

TI

德州仪器

丝印：8601101EA；Package：CDIP；High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

Features • Fully Static Operation • Buffered Inputs • Common Reset • Positive Edge Clocking • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . .

文件：738.58 Kbytes 页数：22 Pages

TI

德州仪器

丝印：8601101EA；Package：CDIP；DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS

2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

文件：275.83 Kbytes 页数：12 Pages

TI

德州仪器

丝印：8601101EA；Package：CDIP；DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS

2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

文件：275.83 Kbytes 页数：12 Pages

TI

德州仪器

丝印：8601101EA；Package：CDIP；High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

Features • Fully Static Operation • Buffered Inputs • Common Reset • Positive Edge Clocking • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . .

文件：738.58 Kbytes 页数：22 Pages

TI

德州仪器

丝印：8601101EA；Package：CDIP；DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS

2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)

文件：275.83 Kbytes 页数：12 Pages

TI

德州仪器

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

Features • Fully Static Operation • Buffered Inputs • Common Reset • Positive Edge Clocking • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . .

文件：738.58 Kbytes 页数：22 Pages

TI

德州仪器

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

文件：347.51 Kbytes 页数：14 Pages

TI

德州仪器

DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS

文件：215.42 Kbytes 页数：12 Pages

TI

德州仪器