Low Skew, 1-to-10 Differential-to-3.3V, 2.5V LVPECL/ECL Fanout Buffer

Features • Ten differential 2.5V, 3.3V LVPECL/ECL output pair • Two selectable differential input pairs • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translates any single ended input signal to

文件：430.88 Kbytes 页数：19 Pages

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Low Skew, 1-to-10 Differential-to-3.3V, 2.5V LVPECL/ECL Fanout Buffer

Features • Ten differential 2.5V, 3.3V LVPECL/ECL output pair • Two selectable differential input pairs • Differential CLKx, nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translates any single ended input signal t

文件：437.42 Kbytes 页数：19 Pages

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LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER

FEATURES • Two differential 2.5V/3.3V LVPECL / ECL bank outputs • Two differential clock input pairs • CLKx, nCLKx pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translates any single ended input signal to 3.3V

文件：290.7 Kbytes 页数：17 Pages

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Low Skew, Dual, 1-to-5, 2.5V/3.3V Differential-to-ECL/LVPECL Fanout Buffer

FEATURES • Two differential 2.5V/3.3V LVPECL / ECL bank outputs • Two differential clock input pairs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translates any single ended input signal to 3.3V

文件：233.14 Kbytes 页数：17 Pages

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Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V/3.3V LVPECL / ECL outputs • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 1GHz • Translates any single ended input signal to 3.3V LVPECL levels with

文件：626.01 Kbytes 页数：17 Pages

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丝印：85311AIL；Package：SOIC；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V/3.3V LVPECL / ECL outputs • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 1GHz • Translates any single ended input signal to 3.3V LVPECL levels with

文件：628.64 Kbytes 页数：18 Pages

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丝印：85311AIL；Package：SOIC；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V/3.3V LVPECL / ECL outputs • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 1GHz • Translates any single ended input signal to 3.3V LVPECL levels with

文件：628.64 Kbytes 页数：18 Pages

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丝印：85311ALF；Package：SOIC；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V/3.3V LVPECL / ECL outputs • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 1GHz • Translates any single ended input signal to 3.3V LVPECL levels with

文件：626.01 Kbytes 页数：17 Pages

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丝印：85311ALF；Package：SOIC；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V/3.3V LVPECL / ECL outputs • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 1GHz • Translates any single ended input signal to 3.3V LVPECL levels with

文件：626.01 Kbytes 页数：17 Pages

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Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V/3.3V LVPECL / ECL outputs • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 1GHz • Translates any single ended input signal to 3.3V LVPECL levels with

文件：628.64 Kbytes 页数：18 Pages

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