82V3001

WAN PLL WITH SINGLE REFERENCE INPUT

82V3001A

WAN PLL With Single Reference Input

The 82V3001A is a WAN PLL with single reference input. It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. The 82V3001A provides eight types of clock signals (C1.5o, C3o, C6o, C2o,; • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces\n• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface\n• Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048 MHz\n• Provides eight types of clock signals: C;

82V3001A

WAN PLL WITH SINGLE REFERENCE INPUT

82V3001APVG8

WAN PLL WITH SINGLE REFERENCE INPUT

82V3001APVG

Package：56-BSSOP（0.295"，7.50mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 应用特定时钟/定时 描述：IC PLL WAN W/SGL REF INP 56SSOP

Renesas Electronics America Inc

82V3001APVG8

Package：56-BSSOP（0.295"，7.50mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：IC PLL WAN W/SGL REF INP 56-SSOP

Renesas Electronics America Inc