28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

文件：770.75 Kbytes 页数：25 Pages

TI

德州仪器

28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

文件：434.7 Kbytes 页数：23 Pages

TI

德州仪器

具有针对负载严重的 DDR2 寄存 DIMM 进行奇偶校验测试的 28 位至 56 位寄存缓冲器

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM is required to drive up to 18 stacked SDRAM loads or two devices per DIMM are required to drive up to 36 stacked SDRAM loads. All inputs are SSTL_18, except the chip-select gate-enable (C • Member of the Texas Instruments Widebus+™ Family\n• 1-to-2 Outputs Support Stacked DDR2 DIMMs\n• Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption\n• Supports SSTL_18 Data Inputs\n• Supports LVCMOS Switching Levels on the Chip-Select Gate-Enable, C;

TI

德州仪器

Package：176-TFBGA；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 专用逻辑器件 描述：IC REGSTR BUFFER 28-56BIT 176BGA

TI

德州仪器

Package：176-TFBGA；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 专用逻辑器件 描述：IC CONFIG REG BUFF 28BIT 176-BGA

TI

德州仪器