28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

1FEATURES 2· Member of the Texas Instruments Widebus+ ™Family · Pinout Optimizes DDR2 DIMM PCB Layout · 1-to-2 Outputs Supports Stacked DDR2 DIMMs · One Device Per DIMM Required · Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption · Output E

文件：532.77 Kbytes 页数：25 Pages

TI

德州仪器

28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

1FEATURES 2· Member of the Texas Instruments Widebus+ ™Family · Pinout Optimizes DDR2 DIMM PCB Layout · 1-to-2 Outputs Supports Stacked DDR2 DIMMs · One Device Per DIMM Required · Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption · Output E

文件：533.08 Kbytes 页数：25 Pages

TI

德州仪器

28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

文件：981.62 Kbytes 页数：26 Pages

TI

德州仪器

28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

文件：434.7 Kbytes 页数：23 Pages

TI

德州仪器

具有地址奇偶校验测试的 28 位至 56 位寄存缓冲器

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM is required to drive up to 18 SDRAM loads or two devices per DIMM are required to drive up to 36 SDRAM loads. All inputs are SSTL_18, except the chip-select gate-enable (CSGEN), control ( • Member of the Texas Instruments Widebus+™ Family\n• 1-to-2 Outputs Supports Stacked DDR2 DIMMs\n• Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption\n• Supports SSTL_18 Data Inputs\n• Supports LVCMOS Switching Levels on the Chip-Select Gate-Enable, ;

TI

德州仪器

28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

1FEATURES 23· Member of the Texas Instruments Widebus+™ Family · Pinout Optimizes DDR2 DIMM PCB Layout · 1-to-2 Outputs Support Stacked DDR2 DIMMs · One Device Per DIMM Required · Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption · Output E

文件：534.25 Kbytes 页数：25 Pages

TI

德州仪器

28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

1FEATURES 23· Member of the Texas Instruments Widebus+™ Family · Pinout Optimizes DDR2 DIMM PCB Layout · 1-to-2 Outputs Support Stacked DDR2 DIMMs · One Device Per DIMM Required · Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption · Output E

文件：533.94 Kbytes 页数：25 Pages

TI

德州仪器

丝印：SB868A；Package：NFBGA；28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

1FEATURES 23· Member of the Texas Instruments Widebus+™ Family · Pinout Optimizes DDR2 DIMM PCB Layout · 1-to-2 Outputs Support Stacked DDR2 DIMMs · One Device Per DIMM Required · Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption · Output E

文件：533.94 Kbytes 页数：25 Pages

TI

德州仪器

丝印：SB868A；Package：NFBGA；28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

1FEATURES 23· Member of the Texas Instruments Widebus+™ Family · Pinout Optimizes DDR2 DIMM PCB Layout · 1-to-2 Outputs Support Stacked DDR2 DIMMs · One Device Per DIMM Required · Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption · Output E

文件：534.25 Kbytes 页数：25 Pages

TI

德州仪器

丝印：SB868A；Package：NFBGA；28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

1FEATURES 23· Member of the Texas Instruments Widebus+™ Family · Pinout Optimizes DDR2 DIMM PCB Layout · 1-to-2 Outputs Support Stacked DDR2 DIMMs · One Device Per DIMM Required · Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption · Output E

文件：534.25 Kbytes 页数：25 Pages

TI

德州仪器