28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

文件：773.58 Kbytes 页数：21 Pages

TI

德州仪器

28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

文件：728.49 Kbytes 页数：21 Pages

TI

德州仪器

28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

文件：773.58 Kbytes 页数：21 Pages

TI

德州仪器

28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

文件：728.49 Kbytes 页数：21 Pages

TI

德州仪器

具有地址奇偶校验的 28 位至 56 位寄存缓冲器

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM is required to drive up to stacked 18 SDRAM loads or two devices per DIMM are required to drive up to 36 stacked SDRAM loads.\n All inputs are SSTL_18, except the chip-select gate-enable ·Member of the Texas Instruments Widebus+™ Family\n ·Pinout Optimizes DDR2 RDIMM PCB Layout\n ·1-to-2 Outputs Supports Stacked DDR2 RDIMMs\n ·High driver strength for heavily loaded DIMMs\n ·Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption\n ·Output;

TI

德州仪器

Package：160-TFBGA；包装：托盘 类别：集成电路（IC） 专用逻辑器件 描述：IC REGSTR BUFF 28-56BIT 160NFBGA

TI2

德州仪器