3.3 Volt ABT octal transparent latch 3-State

DESCRIPTION The 74LVT373 device is designed specifically for low–voltage (3.3V) VCC operation, but can provide a TTL interface to a 5V system environment. The 74LVT373 high-performance BiCMOS device combines zero static and low dynamic power dissipation with high speed and high output drive. FE

文件：75.93 Kbytes 页数：6 Pages

PHI

PHI

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：105.29 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：306.53 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：306.53 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：306.53 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：306.53 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：105.29 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体

Low Voltage Octal Transparent Latch with 3-STATE Outputs

文件：316.77 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体

Low Voltage Octal Transparent Latch with 3-STATE Outputs

文件：316.77 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体

Low Voltage Octal Transparent Latch with 3-STATE Outputs

文件：316.77 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体