Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：105.29 Kbytes 页数：8 Pages

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Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：306.53 Kbytes 页数：12 Pages

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3.3 Volt ABT octal transparent latch 3-State

DESCRIPTION The 74LVT373 device is designed specifically for low–voltage (3.3V) VCC operation, but can provide a TTL interface to a 5V system environment. The 74LVT373 high-performance BiCMOS device combines zero static and low dynamic power dissipation with high speed and high output drive. FE

文件：75.93 Kbytes 页数：6 Pages

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Low Voltage Octal Transparent Latch with 3-STATE Outputs

文件：316.77 Kbytes 页数：10 Pages

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低压八路透明锁存器（带3态输出）

LVT373和LVTH373包含八个带有3态输出的闩锁，适合用于总线结构的系统应用。 当锁存使能(LE)为高电平时，锁存器对于数据而言是透明的。 当LE为低电平时，满足输入时序要求的数据被锁存。 当输出使能(OE#)为低电平时，数据显示在总线上。 当OE#为高电平时，总线输出处于高阻抗状态。 LVTH373数据输入包含总线保持功能，无需外部上拉电阻即可保持未用的输入。 这些八通道闩锁设计用于低电压(3.3V) VCC应用，也可向5V环境提供TTL接口。 LVT373和LVTH373采用先进的BiCMOS技术制造，可实现类似于5V ABT的高速运行，同时又能维持较低的CMOS功耗。 •系统在5V VCC时的输入和输出接口能力\n•总线保持数据输入无需外部上拉电阻即可保持未用的输入(74LVTH373)，另外还提供不含总线保持功能的配置(74LVT373)。\n•允许带电插/拔\n•上电/掉电高阻抗提供无干扰总线负载\n•-32 mA/+64 mA输出源电流/灌电流\n•功能上兼容74系列373\n•静电放电(ESD)性能：人体模型> 2000V机械模型> 200V充电器件模型> 1000V;

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3.3 Volt ABT octal transparent latch 3-State

DESCRIPTION The 74LVT373 device is designed specifically for low–voltage (3.3V) VCC operation, but can provide a TTL interface to a 5V system environment. The 74LVT373 high-performance BiCMOS device combines zero static and low dynamic power dissipation with high speed and high output drive. FE

文件：75.93 Kbytes 页数：6 Pages

PHI

PHI

3.3 Volt ABT octal transparent latch 3-State

DESCRIPTION The 74LVT373 device is designed specifically for low–voltage (3.3V) VCC operation, but can provide a TTL interface to a 5V system environment. The 74LVT373 high-performance BiCMOS device combines zero static and low dynamic power dissipation with high speed and high output drive. FE

文件：75.93 Kbytes 页数：6 Pages

PHI

PHI

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：306.53 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：306.53 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

文件：105.29 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体