3.3V Quad 2-input AND gate

3.3V Quad 2-input AND gate

文件：78.3 Kbytes 页数：10 Pages

PHI

PHI

3.3 V Quad 2-input AND gate

1. General description The 74LVT08 is a quad 2-input AND gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and

文件：213.42 Kbytes 页数：10 Pages

NEXPERIA

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3.3V Quad 2-input AND gate

3.3V Quad 2-input AND gate

文件：78.3 Kbytes 页数：10 Pages

PHI

PHI

3.3 V Quad 2-input AND gate

The 74LVT08 is a quad 2-input AND gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. • Wide supply voltage range from 2.7 V to 3.6 V\n• Overvoltage tolerant inputs to 5.5 V\n• BiCMOS high speed and output drive\n• Direct interface with TTL levels\n• IOFF circuitry provides partial Power-down mode operation\n• Latch-up performance exceeds 500 mA per JESD 78 Class II Level B\n• Compli;

Nexperia

安世

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE AND 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE AND 4CH 2-INP 14TSSOP

Nexperia USA Inc.