74LVT08PWDH资料使用说明书贸易商飞利浦-114ic电子网

首页 >74LVT08PWDH>规格书列表

型号	下载订购	功能描述	制造商上传企业	LOGO
74LVT08PWDH	文件：78.3 Kbytes Page：10 Pages	3.3V Quad 2-input AND gate 3.3V Quad 2-input AND gate 文件：78.3 Kbytes 页数：10 Pages	PHI 飞利浦	PHI
74LVT08	文件：78.3 Kbytes Page：10 Pages	3.3V Quad 2-input AND gate 3.3V Quad 2-input AND gate 文件：78.3 Kbytes 页数：10 Pages	PHI 飞利浦	PHI
74LVT08	文件：213.42 Kbytes Page：10 Pages	3.3 V Quad 2-input AND gate 1. General description The 74LVT08 is a quad 2-input AND gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and 文件：213.42 Kbytes 页数：10 Pages	NEXPERIA 安世	NEXPERIA
74LVT08D	文件：78.3 Kbytes Page：10 Pages	3.3V Quad 2-input AND gate 3.3V Quad 2-input AND gate 文件：78.3 Kbytes 页数：10 Pages	PHI 飞利浦	PHI

更多74LVT08PWDH供应商更新时间2025-11-1 14:30:00