16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuringseparate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. The 74LVC16374A consists of 2 sections of eight positive edge-triggered flip-flops. A clock (CP) input and an output enable (OE

文件：82.1 Kbytes 页数：10 Pages

PHI

PHI

16-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state

General description The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus oriented applications. It consists of two sections of eight positive edge-triggered flip-flop

文件：175.05 Kbytes 页数：19 Pages

恩XP

3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：399.46 Kbytes 页数：7 Pages

RENESAS

瑞萨

3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：399.46 Kbytes 页数：7 Pages

RENESAS

瑞萨

3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：399.46 Kbytes 页数：7 Pages

RENESAS

瑞萨

3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：399.46 Kbytes 页数：7 Pages

RENESAS

瑞萨

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

General description The 74LVC16374A-Q100 and 74LVCH16374A-Q100 are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A-Q100 only) for each flip-flop and 3-state outputs for bus-oriented applications. It consists of two sections of eight positive edge-trig

文件：230.64 Kbytes 页数：14 Pages

NEXPERIA

安世

16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs

文件：918.42 Kbytes 页数：24 Pages

TI

德州仪器

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：333.5 Kbytes 页数：15 Pages

TI

德州仪器

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：392.27 Kbytes 页数：18 Pages

TI

德州仪器