16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/output tolerant; 3-state

DESCRIPTION The 74LVC(H)162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

文件：86.25 Kbytes 页数：16 Pages

PHI

飞利浦

16-bit edge-triggered D-type flip-flop with 30 Ω series termination resistors; 5 V input/output tolerant; 3-state

1. General description The 74LVCH162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The device consists of two sections of 8 edge-triggered flip-flops. A clock (CP) input and an output enable (OE) a

文件：244.33 Kbytes 页数：14 Pages

NEXPERIA

安世

16-bit edge-triggered D-type flip-flop with 30 Ω series termination resistors; 5 V input/output tolerant; 3-state

1. General description The 74LVCH162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The device consists of two sections of 8 edge-triggered flip-flops. A clock (CP) input and an output enable (OE) a

文件：244.33 Kbytes 页数：14 Pages

NEXPERIA

安世

16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/output tolerant; 3-state

DESCRIPTION The 74LVC(H)162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

文件：86.25 Kbytes 页数：16 Pages

PHI

飞利浦

16-bit edge triggered D-type flip-flop with 30 ohmseries termination resistors; 5 V input/output tolerant; 3-state

DESCRIPTION The 74LVC(H)162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

文件：86.25 Kbytes 页数：16 Pages

PHI

飞利浦

3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：262.97 Kbytes 页数：7 Pages

RENESAS

瑞萨

3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD

FEATURES: • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4μ W typ. static) • All inputs, outputs, and I/O are 5V to

文件：262.97 Kbytes 页数：7 Pages

RENESAS

瑞萨

3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIPFLOP

文件：106.62 Kbytes 页数：6 Pages

IDT

3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIPFLOP

文件：106.62 Kbytes 页数：6 Pages

IDT

3.3V CMOS 16-Bit Edge-Triggered D-Type Flip-Flop with 3-State Outputs, 5.0V Tolerant I/O, and Bus-Hold

The 74LVCH162374A 16-bit high-speed, low power edge-triggered D-type flip-flop is ideal for use as a buffer register for data synchronization and storage. It can operate as two 8-bit registers or one 16-bit register with common clock. All pins of the 74LVCH162374A can be driven from either 3.3V or 5 Typical tSK(o) (Output Skew) ESD > 2000V per MIL-STD-883, Method 3015\n> 200V using machine model (C = 200pF, R = 0)\nVCC = 3.3V ± 0.3V, Normal Range\nVCC = 2.7V to 3.6V, Extended Range\nCMOS power levels (0.4 uW typ. static)\nAll inputs, outputs, and I/O are 5V tolerant\nAvailable in 48 pin TSSOP p;

Renesas

瑞萨