Dual D-Type Positive Edge-Triggered Flip-Flop with Set and Reset

The 74LVC74 is a dual D-type flip-flop positive edge-triggered with set and reset. This device accepts a wide supply voltage range from 1.2V to 3.6V. nD are individual data inputs, nCP are clock inputs, nSD and nRD are set inputs, nQ and nQ are complementary outputs.\nThe set and reset are non-synch • Wide Supply Voltage Range: 1.2V to 3.6V\n\n• Inputs Accept Voltages up to 5V\n\n• CMOS Low Power Consumption\n\n• Direct Interface with TTL Levels\n\n• -40℃ to +125℃ Operating Temperature Range\n\n• Available in a Green TSSOP-14 Package;

SGMICRO

圣邦股份

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

文件：99.08 Kbytes 页数：10 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive-edge trigger

General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Informati

文件：111.03 Kbytes 页数：16 Pages

恩XP

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input

文件：266.16 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input

文件：266.16 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Informati

文件：111.03 Kbytes 页数：16 Pages

恩XP

Dual D-type flip-flop with set and reset; positive-edge trigger

General description The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock in

文件：722.92 Kbytes 页数：18 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input

文件：266.16 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Informati

文件：111.03 Kbytes 页数：16 Pages

恩XP

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

文件：99.08 Kbytes 页数：10 Pages

PHI

PHI