74LVC374: Low Voltage CMOS Octal D Flip-Flop

The 74LVC374A is a high performance, non-inverting octal D-type flip-flop operating from a 1.2 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 Designed for 1.2 to 3.6 V VCC Operation\n5 V Tolerant − Interface Capability With 5 V TTL Logic\nSupports Live Insertion and Withdrawal\nIOFF Specification Guarantees High Impedance When VCC = 0 V\n24 mA Output Sink and Source Capability\nNear Zero Static Supply Current in All Three Logic States (10;

ONSEMI

安森美半导体

Low-Voltage CMOS Octal Buffer

Low-Voltage CMOS Octal D-Type Flip-Flop With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC374A is a high performance, non−inverting octal D−type flip−flop operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input

文件：102 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State

DESCRIPTION The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

文件：101.27 Kbytes 页数：12 Pages

PHI

PHI

OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS

Description The 74LVC374A provides eight edge-triggered D-type flip-flops featuring 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirecti

文件：444.4 Kbytes 页数：10 Pages

DIODES

美台半导体

OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE

DESCRIPTION The 74LVC374A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a clock input (CK) and an output enable input (OE)

文件：298.1 Kbytes 页数：14 Pages

STMICROELECTRONICS

意法半导体

Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

1. General description The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the

文件：271.57 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

1. General description The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the

文件：271.57 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

1. General description The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the

文件：271.57 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State

DESCRIPTION The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

文件：101.27 Kbytes 页数：12 Pages

PHI

PHI

Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State

DESCRIPTION The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

文件：101.27 Kbytes 页数：12 Pages

PHI

PHI