Single D-type flip-flop; positive-edge trigger

The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop.\n Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable opera • Wide supply voltage range from 1.65 V to 5.5 V\n• High noise immunity\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• ±24 mA outpu;

Nexperia

安世

丝印：VT；Package：SOT1226-3；Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

文件：277.35 Kbytes 页数：19 Pages

NEXPERIA

安世

Package：4-XFDFN 裸露焊盘；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 1BIT 5X2SON

Nexperia USA Inc.

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

文件：657.15 Kbytes 页数：22 Pages

TI

德州仪器

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

文件：513.809 Kbytes 页数：16 Pages

TI

德州仪器

Single Positive-Edge-Triggered D-Type Flip-Flop

文件：881.23 Kbytes 页数：23 Pages

TI

德州仪器